EC 2203 - DIGITAL ELECTRONICS |
UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES |
Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem -
Principle of Duality - Boolean expression - Minimization of Boolean expressions ––
Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map
Minimization – Don’t care conditions - Quine-McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NORImplementations
of Logic Functions using gates, NAND–NOR implementations – Multi
level gate implementations- Multi output gate implementations. TTL and CMOS Logic
and their characteristics – Tristate gates. |
UNIT II COMBINATIONAL CIRCUITS |
Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor - Parallel
binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial
Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/
Demultiplexer – decoder - encoder – parity checker – parity generators - code
converters - Magnitude Comparator. |
UNIT IIISEQUENTIAL CIRCUITS |
Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation
–Application table – Edge triggering – Level Triggering – Realization of one flip flop
using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter –
Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down
counters – Programmable counters – Design of Synchronous counters: state diagram-
State table –State minimization –State assignment - Excitation table and maps-Circuit
implementation - Modulo–n counter, Registers – shift registers - Universal shift registers
– Shift register counters – Ring counter – Shift counters - Sequence generators. |
UNIT IVMEMORY DEVICES |
Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM –
EAPROM, RAM – RAM organization – Write operation – Read operation – Memory
cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell-
Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic
Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) - Field
Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits
using ROM, PLA, PAL |
UNIT VSYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS |
Synchronous Sequential Circuits: General Model – Classification – Design – Use of
Algorithmic State Machine – Analysis of Synchronous Sequential Circuits. Asynchronous Sequential Circuits:Design of fundamental mode and pulse mode
circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits –
Design of Hazard Free Switching circuits. Design of Combinational and Sequential
circuits using VERILOG |
Text Book |
1. Mark Allen Weiss, “Data Structures and Algorithm Analysis in C”, 3rd ed, Pearson
Education Asia, 2007.
2. E. Balagurusamy, “ Object Oriented Programming with C++”, McGraw Hill Company
Ltd., 2007. |
References |
REFERENCES:
1. Michael T. Goodrich, “Data Structures and Algorithm Analysis in C++”, Wiley student
edition, 2007.
2. Sahni, “Data Structures Using C++”, The McGraw-Hill, 2006.
3. Seymour, “Data Structures”, The McGraw-Hill, 2007.
4. Jean – Paul Tremblay & Paul G.Sorenson, An Introduction to data structures with
applications, Tata McGraw Hill edition, II Edition, 2002.
5. John R.Hubbard, Schaum’s outline of theory and problem of data structure with C++,
McGraw-Hill, New Delhi, 2000.
6. Bjarne Stroustrup, The C++ Programming Language, Addison Wesley, 2000.
7. Robert Lafore, Object oriented programming in C++, Galgotia Publication |
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