Simple Design exercises:
1. Half adder, Full adder, Subtractor Flip Flops, 4bit comparator.
2. Parity generator
3. Bit up/down counter with load able count
4. Decoder and encoder
5. 8 bit shift register
6. 8:1 multiplexer
7. Test bench for a full adder
8. Barrel shifter
9. N by m binary multiplier
10. RISC CPU (3bit opcode, 5bit address).
TOOLS :
Xilinx Tools/ Synopsis Tools/ Cadence Tools/ Model SIM/ Leonardo Spectrum Tools/VIS/SIS Tools to be used.