8 CS 2-CAD FOR VLSI DESIGN |
Units: I |
Modern digital systems, complexity and diversity of digital systems, productivity gap and need for CAD tools. Introduction to
steps and CAD flow for designing with ASIC and FPGA.
|
Units: II |
Introduction to VHDL, background, VHDL requirement, Elements of VHDL, top down design, convention and syntax, basic
concepts in VHDL i.e. characterizing H/W languages, objects, classes, and signal assignments. |
Units: III |
Structural specification of H/W- Parts library, Wiring, modeling, binding alternatives, top down wiring. Design organization
and parameterization. Type declaration, VHDL operators.
|
Units: IV |
VHDL subprogram parameters, overloading, predefined attributes, user defined attributes, packaging basic utilities. VHDL as
a modeling language- bi-directional component modeling, multi mode component modeling,
|
Units: V |
Examples of VHDL synthesis subsets- combinational logic synthesis, sequential circuit synthesis, state machine synthesis.
VHDL language grammar. Introduction to synthetic circuits and circuit repositories.
|
|