Introduction to VLSI, circuits Asics and Moore’s Law. Microelectronic Design, Styles,
four phases in creating Microelectronics chips computer Aided Synthesis and
Optimization. Algorithms Review of Graph Definitions and Notations Decision and
Optimization Problems, Shortest and Longest Path Problems, Vertex Cover, Graph,
Coloring, Clique covering and partitioning Algorithms Boolean Algebra and
Representation of Boolean Functions, binary Decision diagrams. Satisfiability and cover
problems.
Units: II
Hardware Modeling: Introduction to Hardware Modeling Language, State Diagrams.
Data flow and Sequencing Graphs. Compilation and Behavioral Optimization
Techniques. Circuits Specifications for Architectural Synthesis Resources and
constraints. Fundamental Architectural Synthesis Problems Temporal Domain
Scheduling Spatial Domain Binding Hierarchical Models and Synchronization Problem.
Area and performance estimation-Resource Dominated circuits and General Circuits.
Units: III
Scheduling Algorithms: Model for Scheduling Problems, Scheduling without Resource,
Constraints-Unconstrained Scheduling ASAP Scheduling Algorithms Latency.
Constrained Scheduling. ALAP scheduling. Under Timing Constraints and Relative
Scheduling with Resource Constraints Integer Linear Programming Model,
Multiprocessor Scheduling, Heuristic Scheduling Algorithms (List Scheduling). Force
Directed Scheduling.
Units: IV
Two Level Combination Logic Optimization: Logic Optimization Principles-Definitions,
Exact Logic Minimization, Heuristic, Logic Minimization, and Testability Properties
Operations on Two level logic Cover-positional Cube Notation, Functions with
Multivolume inputs and list oriented manipulation. Algorithms for logic minimization.
Units: V
Introduction to VHDL: VHDL History and capabilities program Structure of VHDL
Entity, Architecture and package Declarations. Basic Language Elements, Identifier,
Data objects, Data Types and Operator Behavioral Modeling- process variable
Assignment, Signal Assignment and Wait Statements. Assertion Loop, if, case and
next Statement Block and concurrent Assertion statements structural specifications of
Hardware-inverter, Nand Gate Models, Comparator and Test Bench Modeling.