06EC665 - LOW POWER VLSI DESIGN |
PART – A |
UNIT – I |
Introduction, Sources of power dissipation, designing for low power.
Physics of power dissipation in MOSFET devices – MIS Structure, Long
channel and sub-micron MOSFET, Gate induced Drain leakage. |
UNIT – II |
Power dissipation in CMOS – Short circuit dissipation, dynamic dissipation,
Load capacitance. Low power design limits - Principles of low power design,
Hierarchy of limits, fundamental limits, Material, device, circuit and system
limits. |
UNIT – III and IV |
SYNTHESIS FOR LOW POWER: Behavioral, Logic and Circuit level
approaches, Algorithm level transforms, Power-constrained Least squares
optimization for adaptive and non-adaptive filters, Circuit activity driven
architectural transformations, voltage scaling, operation reduction and
substitution, pre- computation, FSM and Combinational logic, Transistor
sizing. |
PART – B |
UNIT – V and VI |
DESIGN AND TEST OF LOW-VOLTAGE CMOS CIRCUITS: Introduction, Design style, Leakage current in Deep sub-micron transistors,
device design issues, minimizing short channel effect, Low voltage design
techniques using reverse Vgs, steep sub threshold swing and multiple
threshold voltages, Testing with elevated intrinsic leakage, multiple supply
voltages. |
UNIT – VI |
Detection and estimation, Model of DCS, Gram-Schmidt Orthogonalization
procedure, geometric interpretation of signals, response of bank of correlators
to noisy input. |
UNIT – VII |
LOW ENERGY COMPUTING: Energy dissipation in transistor channel,
Energy recovery circuit design, designs with reversible and partially
reversible logic, energy recovery in adiabatic logic and SRAM core, Design
of peripheral circuits – address decoder, level shifter and I/O Buffer, supply
clock generation. |
UNIT – VIII |
SOFTWARE DESIGN FOR LOW POWER: Introduction, sources of
power dissipation, power estimation and optimization. |
REFERENCE |
TEXT BOOKS: |
1. Low-Power CMOS VLSI Circuit Design, Kaushik Roy and Sharat
C Prasad, Wiley Inter science, 2000. |
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