06EC45 - FUNDAMENTALS OF HDL |
PART – A |
UNIT – I :Introduction: |
Why HDL? , A Brief History of HDL, Structure of HDL
Module, Operators, Data types, Types of Descriptions, simulation and
synthesis, Brief comparison of VHDL and Verilog |
UNIT – II :Data –Flow Descriptions: |
Highlights of Data-Flow Descriptions, Structure
of Data-Flow Description, Data Type – Vectors |
UNIT – III :Behavioral Descriptions: |
Behavioral Description highlights, structure of
HDL behavioral Description, The VHDL variable –Assignment Statement,
sequential statements.
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UNIT – IV :Structural Descriptions: |
Highlights of structural Description, Organization
of the structural Descriptions, Binding, state Machines, Generate, Generic,
and Parameter statements.
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PART – B |
UNIT – V:Procedures, Tasks, and Functions: |
Highlights of Procedures,
tasks, and Functions, Procedures and tasks, Functions.
Advanced HDL Descriptions: File Processing, Examples of File Processing |
UNIT – VI :Mixed –Type Descriptions: |
Why Mixed-Type Description? VHDL User-
Defined Types, VHDL Packages, Mixed-Type Description examples
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UNIT – VII :Mixed –Language Descriptions: |
Highlights of Mixed-Language
Description, How to invoke One language from the Other, Mixed-language
Description Examples, Limitations of Mixed-Language Description
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UNIT – VIII:Synthesis Basics: |
Highlights of Synthesis, Synthesis information from Entity
and Module, Mapping Process and Always in the Hardware Domain.
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REFERENCE |
TEXT BOOKS: |
1. HDL Programming (VHDL and Verilog)- Nazeih M.Botros-
Dreamtech Press
2. (Available through John Wiley – India and Thomson Learning) 2006
Edition |
Reference Books |
1. Verilog HDL –Samir Palnitkar-Pearson Education
2. VHDL -Douglas perry-Tata McGraw-Hill
3. A Verilog HDL Primer- J.Bhaskar – BS Publications
4. Circuit Design with VHDL-Volnei A.Pedroni-PHI
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