06ESL38 - Logic Design Lab Regulation 2006 - 2007 |
1. Simplification, realization of Boolean expressions using logic gates/Universal gates.
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2. Realization of Half/Full adder and Half/Full Subtractors using logic gates.
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3.
(i) Realization of parallel adder/Subtractors using 7483 chip
(ii) BCD to Excess-3 code conversion and vice versa.
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4. Realization of Binary to Gray code conversion and vice versa.
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5. MUX/DEMUX – use of 74153, 74139 for arithmetic circuits and code converter.
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6. Realization of One/Two bit comparator and study of 7485 magnitude comparator.
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7. Use of a) Decoder chip to drive LED display and b) Priority encoder.
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8. Truth table verification of Flip-Flops:
(i) JK Master slave
(ii) T type and
(iii) D type.
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9. Realization of 3 bit counters as a sequential circuit and MOD – N
counter design (7476, 7490, 74192, 74193).
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10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.
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11. Wiring and testing Ring counter/Johnson counter.
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12. Wiring and testing of Sequence generator.
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