06CS843 - Arm Based System Design |
PART – A |
UNIT 1 |
INTRODUCTION: The RISC design philosophy; The ARN design
philosophy; Embedded system hardware and software. ARM processor
fundamentals: Registers; Current Program Status Register; Pipeline;
Exceptions, interrupts and the Vector Table; Core extensions; Architecture
revisions; ARM processor families. |
UNIT 2 |
ARM INSTRUCTION SET AND THUMB INSTRUCTION SET: ARM
instruction set: Data processing instructions; Branch instructions; Load-store
instructions; Software interrupt instruction; Program Status Register
functions; Loading constants; ARMv5E extensions; Conditional execution.
Thumb instruction set: Thumb register usage; ARM –Thumb interworking;
Other branch instructions; Data processing instructions; Single-Register
Load-Store instructions; Multiple-Register Load-Store instructions; Stack
instructions; Software interrupt instruction. |
UNIT 3 |
WRITING AND OPTIMIZING ARM ASSEMBLY CODE: Writing
assembly code; Profiling and cycle counting; Instruction scheduling; Register
allocation; Conditional execution; Looping constructs; Bit manipulation;
Efficient switches; Handling unaligned data. |
UNIT 4 |
OPTIMIZED PRIMITIVES: Double-precision integer multiplication;
Integer normalization and count leading zeros; Division; Square roots;
Transcendental functions; Endian reversal and bit operations; Saturated and
rounded arithmetic; Random number generation. |
PART – B |
UNIT 5 |
EXCEPTION AND INTERRUPT HANDLING: Exception handling;
Interrupts and interrupt handling schemes. |
UNIT 6 |
CACHES: The memory hierarchy and the cache memory; Cache
architecture; Cache policy; Coprocessor 15 and cache; Flusing and cleaning
cache memory; Cache lockdown; Caches and software performance. |
UNIT 7 |
MEMORY – 1: Memory Protection Units: Protected regions; Initializing the
MPU, cache and write buffer; Demonstration of an MPU system. Memory
Management Units: Moving from MPU to an MMU; How virtual memory
works; Details of the ARM MMU. |
UNIT 8 |
MEMORY – 2: Page tables; The translation look aside buffer; Domains and
memory access permission; The caches and write buffer; Coprocessor 15 and
MMU configuration; The fast context switch extension. |
REFERENCE |
TEXT BOOKS: |
1. ARM System Developer’s Guide – Designing and Optimizing
System Software – Andrew N. Sloss, Dominic Symes, Chris
Wright, Elsevier, 2004.
|
Reference Books |
1. ARM Architecture Reference Manual – David Seal (Editor), 2nd
Edition, Addison-Wesley, 2001.
2. ARM System-on-Chip Architecture – Steve Furber, 2nd Edition,
Addison-Wesley, 2000. |