Digital Logic And Computer Systems Organization- JNTU Kakinada First Year Syllabus 2009 |
UNIT-I |
Digital Components and Data Representation: Learning Goals, Introduction, Numbering Systems, Decimal to
Binary Conversion, Binary Coded Decimal Numbers, Weighted Codes, Self-Complementing Codesm, Cyclic
Codes, Error Detecting Codes, Error Correcting Codes, Hamming Code for Error Correction, Alphanumeric Codes,
ASCII Code, Indian Script Code for Information Interchange (ISCII), Representation of Multimedia Data,
Representation of Pictures, Representation of Video, Representation of Audio
Boolean Algebra and Logic Gates: Learning Goals, Introduction, Postulates of Boolean Algebra, Basic Theorems
of Boolean Algebra, Duality Principle, Theorems, Precedence of operators, Venn Diagram , Boolean Functions and
Truth Tables, Canonical Forms for Boolean Functions, Binary Operators and Logic Gates, Simplifying Boolean
Expressions, Veitch-Karnaugh Map Method, Four Variable Karnaugh Map, Incompletely Specified Function,
Quine-McCluskey Procedure
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UNIT-II |
Digital logic circuits: Combinatorial Switching Circuits,: Introduction, Combinatorial Circuit Design Procedure,
Integrated NAND-NOR Gates, CMOS Transistor Gates, NAND-NOR Gates with CMOS Transistors, Open Drain
and Tri-state Gates, Wired AND Gate, Driving a Bus from Many Sources, Tri-state Gates, Realization of Boolean
Expressions Using NAND/NOR Gates, Combinatorial Circuits Commonly Used in Digital Systems, Design of
Combinatorial Circuits with Multiplexers, Programmable Logic Devices, Realization with FPLAs, Realization with
PALs
Sequential Switching Circuits: Types, Flip-Flops, Counters, Modelling Sequential Circuits – FSM. Synthesis of
synchronous, Binary counters.
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UNIT – III |
Arithmetic and Logic Unit: Learning Goals, Introduction, Binary Addition, Binary Subtraction, Complement
Representation of Numbers, Addition/Subtraction of Numbers in 1’s Complement Notation, addition/Subtraction of
Numbers in Two’s Complement Notation, Binary Multiplication, Multiplication of signed Numbers, Binary
division, Integer Representation, Floating Point Representation of Numbers, Binary Floating Point Numbers, IEEE
Standard Floating Point Representation, Floating Point addition/Subtraction, Floating Point Multiplication, Floating
Point Division, Floating Point Arithmetic Operations, Logic Circuits for Addition/Subtraction, Half- and Full-Adder
Using Gates, A Four-bit Adder, MSI arithmetic Logic Unit, A Combinatorial Circuit for Multiplication
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UNIT – IV |
Central Processing Unit: Learning Goals, Introduction, Operation Code Encoding and Decoding, Instruction Set
and Instruction Formats, Instruction set, Instruction Format, Addressing Modes, Base Addressing, Segment
Addressing, PC Relative Addressing, Indirect addressing, How to Encode Various Addressing Modes, Register Sets,
Clocks and Timing, CPU Buses, Dataflow, Data Paths and Microprogramming, Control Flow, Summary of CPU
Organization.
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UNIT – V |
Micro programmed Control: Control Memory, Address Sequencing, Conditional Branching, Mapping of
Instruction, Subroutines, Micro program Example, Computer Configuration, Microinstruction Format, Symbolic
Microinstructions, The Fetch Routine, Symbolic Micro program, Binary Micro program , Design of Control Unit,
Micro program Sequencer
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UNIT – VI |
Memory Organization: Learning Goals, Introduction, Memory Parameters, Semiconductor Memory Cell, Dynamic
Memory Cell, Static Memory Cell, Static Memory Cell, Writing data In Memory Cell, Reading the Contents of Cell,
IC Chips for Organization of RAMs , 2D Organization of Semiconductor Memory, 2.5D Organization of Memory
Systems, Dynamic Random Access Memory, Error Detection and Correction in Memories, Read Only Memory,
Dual-Ported RAM, Enhancing Speed and Capacity of Memories, Program Behaviour and Locality Principle, A
Two-Level Hierarchy of Memories, Cache in Memory Organization, Design and Performance of Cache Memory
System, Virtual Memory-Another Level in Hierarchy, address Translation, Page Replacement, Page Fetching, Page
size, fast address Translation , Page Tables.
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UNIT – VII |
Input-Output Organization: Learning Goals, Introduction, device Interfacing, Overview of I/O Methods, Program
Controlled Data Transfer, Interrupt Structures, Single level Interrupt Processing, Handling Multiple Interrupts,
Interrupt Controlled data Transfer, Software Polling, Bus Arbitration, Daisy Chaining, Vectored Interrupts, Multiple
Interrupt Lines, VLSI Chip Interrupt Controller, Programmable Peripheral Interface Unit, DMA Based Data
Transfer, Input/output (I/O) Processors, Bus Structure, Structure of a Bus Types of Bus, Bus Transaction Type ,
Timings of Bus Transactions, Bus Arbitration, some Standard Buses, Serial Data Communication, Asynchronous
Serial data communication, Asynchronous Communication Interface Adapter (ACIA), Digital Modems, Local area
Networks, Ethernet Local area Network-Bus Topology, Ethernet Using star Topology, Wireless LAN, Client-Server
Computing Using LAN.
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UNIT – VIII |
Pipeline and Vector Processing: Parallel Processing, Pipelining-General Considerations, Arithmetic Pipeline,
Instruction Pipeline, Ex: Four-Segment Instruction Pipeline, Data Dependency, Handling of Branch Instructions,
RISC Pipeline, Ex: Three-Segment Instruction Pipeline, Delayed load, Delayed Branch, Vector Processing, Vector
Operations, Matrix Multiplication Memory Interleaving Supercomputers, Array Processors, Attached Array
Processor, SIMD Array Processor
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REFERENCES |
Text Books: |
1. Digital Logic and Computer Organization, Rajaraman, Radhakrishnan, PHI, 2006
2. Computer System Architecture, 3rd ed ., M. Morris Mano, PHI, 1994
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Reference Books |
1. Computer Organization, 5th ed., Hamacher, Vranesic and Zaky, TMH ,2002
2. Computer System Organization & Architecture, John D. Carpinelli, Pearson, 2008
3. Computer System Organization, Naresh Jotwani, TMH, 2009
4. Computer Organization & Architecture: Designing for Performance, 7th ed., William Stallings, PHI, 2006
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